Part 3 of 3: Trends in advanced IC Packaging

Here’s a book excerpt from “Advanced MEMS Packaging,” written by experts in the field. The book details the latest cutting-edge microelectromechanical systems (MEMS) packaging techniques such as low-temperature bonding and 3-D packaging. It can certainly serve as a valuable reference for those faced with the challenging problems created by MEMS devices and packaging. Part 3 covers advanced MEMS packaging. 2.3 Advanced MEMS Packaging Advanced MEMS packaging usually involves at least three wafers, namely, the MEMS device wafer, the ASIC wafer, and the cavity-cap wafer. This section examines the design and processing of 10 different configurations of 3D MEMS packaging.⁵³ These packages are supposed to yield very low-cost, high-performance packaging with a small footprint.

2.3.1 3D MEMS WLP: Designs and Materials Figure 2-31 shows nine different combinations (designs) of 3D MEMS packaging from the MEMS wafer (with either wire-bonding pads, solder-bumped TSV substrate, or solder-bumped flip-chip without TSV), the ASIC wafer (with or without TSV), and the cavity-cap wafer (with or without TSV).⁵³ Case 1: The MEMS device is die attached and then wire bonded on the ASIC chip or wafer. The cavity-cap chip/wafer is attached to the ASIC chip/wafer with a sealing ring, as shown in Fig. 2-32. The signal lines go through beneath the sealing ring to the wirebonding pad on the ASIC chip periphery. Another set of wirebonding pads connects the MEMS/ASIC 3D stack to either a substrate in a package or on a PCB. Case 2: The micro-solder-bumped MEMS device with a TSV substrate is first attached to the ASIC, as shown in Fig. 2-33. The rest is the same as in case 1. Case 3: The solder-bumped flip-chip MEMS device is first attached on the ASIC, as shown in Fig. 2-34. The rest is the same as in case 1. Case 4: The MEMS device is die attached and wire bonded on the ASIC chip with TSV and ordinary solder bumps, as shown in Fig. 2-35. A cavity cap is attached on the ASIC with a sealing ring. The MEMS/ASIC 3D stack is then attached (solder refl owed) to a substrate in a package or on a PCB. Case 5: The micro-solder-bumped MEMS device with a TSV substrate is first attached to the ASIC chip with TSV and ordinary solder bumps, as shown in Fig. 2-36. The rest is the same as in case 4. Case 6: The solder-bumped MEMS device is first attached to the TSV ASIC with ordinary solder bumps, as shown in Fig. 2-37. The rest is the same as in case 5. Case 7: The MEMS device is die attached and then wire bonded on the ASIC. The cavity cap with TSV and ordinary solder bumps is attached to the ASIC with a sealing ring, as shown in Fig. 2-38. Then the whole 3D carrier is attached (solder refl owed) to a substrate in a package or on a PCB. Case 8: The micro-solder-bumped MEMS device with TSV substrate is first attached to the ASIC as shown in Fig. 2-39. The rest is the same as in case 7. Case 9: The solder-bumped MEMS device is first attached to the ASIC as shown in Fig. 2-40. The rest is the same as in case 7. Case 10: The MEMS device is attached to the ordinary solder bumped TSV ASIC with a sealing ring, as shown in Fig. 2-41. Then the whole 3D stack is attached (solder reflowed) to a substrate in a package or on a PCB. 2.3.2 3D MEMS WLP: Processes There are many different processes to assemble these 10 MEMS SiPs. For example, the assembly process shown in Fig. 2-42 can be applied to cases 1 through 3; Fig. 2-43, to cases 4 to 6; and Fig. 2-44, to cases 7 to 9.53 Case 10 will be discussed later. As mentioned earlier, the MEMS wafer can be fabricated either with wire-bonding pads or TSV and solder bumps or a solder-bumped flip-chip, as shown in Figs. 2-42 through 2-44. These are followed by releasing (etching) the MEMS wafer and singulation. For 3D MEMS packaging with lateral electrical feed-through (cases 1, 2, and 3), there is no TSV in both the ASIC and cap wafers (see Fig. 2-42). In these cases, cavities should be formed in the cap wafer by either KOH etching or use of a laser. Then one performs the bonding of the MEMS device (chip) to the ASIC wafer (C2W). This will be followed by bonding of the cavity-cap wafer to the ASIC wafer (W2W). Finally, the bonded wafers are singulated into individual units, which are ready to be wire bonded on the substrate of a package or on a PCB, as shown in Fig. 2-45. For both cases, encapsulant is recommended. For 3D MEMS packaging with vertical electrical feed-through in the ASIC chip (cases 4, 5, and 6), the TSV must be fabricated on the ASIC wafer before C2W bonding, as shown in Fig. 2-43. After the W2W (cap-to-ASIC) bonding, wafer bumping should be performed on the bottom side of the ASIC wafer. After singulations, the individual units can be soldered on the substrate of either a package or a PCB, as shown in Fig. 2-46. For the PCB case, underfill is necessary for the reliability of the solder joints. For the solder-bumped flip-chip-in-package case, use of underfill depends on the substrate material. If it is made of ceramic, then underfill is optional. However, if it is an organic substrate, then underfill is a must. For 3D MEMS packaging with vertical electrical feed-through in the package cap (cases 7, 8, and 9), the TSV and cavity must be fabricated on the cap wafer before W2W bonding, as shown in Fig. 2-44. After W2W bonding, wafer bumping should be performed on the bottom side of the cap wafer. The rest is the same as in cases 4 through 6, and Fig. 2-47 shows an example of the complete 3D MEMS packaging with vertical electrical feed-through in the package cap. In the food chain of electronic products, packaging is a downstream process (i.e., the packaging people cannot be or are not in a proactive position and cannot say too much), and the packaging people just package whatever is given them by the semiconductor people (i.e., our job starts from the wafers). Case 10 (see Fig. 2-41) is a very low-cost, high-performance 3D MEMS package.⁵³ However, in order to make it, the MEMS device (chip) must be much larger (to make space for the sealing ring) than that packages in cases 1 through 9 with a cavity cap. Thus, from a semiconductor points of view, this is a very bad idea because many fewer MEMS devices can be produced on the same size MEMS wafer. Editor’s notes: — Part 1 of 3: Trends in advanced IC packaging — Part 2 of 3: Trends in advanced IC packaging — Click here for additional information about the book or to purchase. Excerpted from Advanced MEMS Packaging by John Lau, et al (McGraw-Hill; 2009) with permission from McGraw-Hill. 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