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TI multicore SoC delivers 5x performance

Friday, February 19, 2010
By Gina Roos

Dallas, Tex. — Aimed at simplifying the design of communications infrastructure equipment, Texas Instruments Inc. (TI) has unveiled its system-on-a-chip (SoC) architecture based on its multicore digital signal processors (DSPs) that integrate fixed and floating point capabilities at the 2010 Mobile World Congress. Running at up to 1.2 GHz and providing an engine with up to 256 GMACS and 128 GFLOPS, the multicore SoCs deliver over five times the performance and twice the memory per core of existing solutions in the market, says TI.

The new architecture offers vendors a common platform to accelerate the development of infrastructure products such as wireless base stations, media gateways and video infrastructure equipment, says TI. The product family will include a range of devices starting with four-core device for wireless base stations and an eight-core device for media gateway and networking applications.

ti-multicoresoc

Other features include direct communication between cores and memory access with TI’s Multicore Navigator, a 2 terabit per second on-chip switch fabric (TeraNet 2), a Multicore Shared Memory Controller that allows faster on-chip and external memory access, and high-performance layer 1, layer 2 and network co-processors.

TI offers a suite of tools, application-specific software libraries and platform software to help speed up the designer’s development cycle and to provide more effective debug and analysis.

Availability: Products from the new multicore portfolio will begin sampling in the second half of 2010.
Resources: Video, multicore entitlement white paper, LTE white paper, presentation, multicore microsite, and communications infrastructure products.

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