Part 2 of 3: Trends in advanced IC packaging

Here’s a book excerpt from “Advanced MEMS Packaging,” written by experts in the field. The book details the latest cutting-edge microelectromechanical systems (MEMS) packaging techniques such as low-temperature bonding and 3-D packaging. It can certainly serve as a valuable reference for those faced with the challenging problems created by MEMS devices and packaging. Part 2 continues the discussion on advanced IC packaging.

2.2.4 Thermal Management of 3D IC SiP with TSV
As mentioned earlier, thermal management is one of the critical issues of 3D IC integration. Thus low-cost and effective thermal management design guidelines and solutions are desperately needed for widespread use of 3D IC integration. Based on the theory of heat transfer, this section examines the thermal performance of 3D stacking of up to eight copper-filled TSV chips. The results are plotted in useful design charts for engineering practice convenience, and design guidelines are also provided.²⁰

In order to have a miniature product with low-profit and small form-factor components, the chip thickness in a 3D stacked component must be very thin (e.g., 50 um or less). Unfortunately, chip temperature and the hot-spot temperature in a chip increase with reductions in chip thickness, which poses significant thermal management challenges. This section also presents heat-transfer analysis of a (5 x 5 mm) chip with different thicknesses (from 10 to 200 um) subjected to various heat sources. In addition, the thermal coupling effects of a (5 x 5 x 0.05 mm) chip subjected to heat sources at various locations are presented. Again, useful design charts and design guidelines relating the important parameters are provided.

Even with the most effective software and advanced high-speed hardware, it is impossible to model all the TSVs in a 3D IC integration SiP. Therefore, this section develops empirical equations for the equivalent thermal conductivity of a copper-filled TSV chip with various TSV diameters, pitches, and aspect ratios through detailed 3D heat-transfer Computational Fluid Dynamic (CFD) analysis. These equations then are used (for each TSV chip as a lumped block) to perform all the simulations reported herein.

Equivalent Thermal Conductive of TSV Chips

Figure 2-18 is a schematic of a 3D IC integration of eight copper filled TSV chips. The top-layer chip does not (and does not need to) have a TSV. These chips are connected through microbumps, and the bottom TSV chip is also connected to the organic printed circuit board (PCB) by ordinary flip-chip solder bumps. Owing to the large thermal expansion mismatch between the silicon chip and the organic PCB, underfill is needed to cement the bottom chip (and the stack) to the PCB so that the solder joints are reliable. Underfill may not be necessary between all the TSV chips.

As mentioned earlier, this section determines the equivalent thermal conductivity of the copper-filled TSV chips through detailed 3D CFD analysis. One of the TSV chip is shown schematically in the upper right-hand corner of Fig. 2-18. It can be seen that unlike the thermal conductivity of an ordinary silicon chip [150 W/(m • °C)], which is isotropic, the thermal conductivity of a copper-filled TSV silicon chip is anisotropic; that is, the thermal conductivity in the xy-planar directions (k_eq,x =k_eq,y) is not equal to that in z-normal direction (k_eq,z). [The thermal conductivity of copper is 390 W/(m • °C).] The approaches for extracting k_eq,x = k _eq,y and k_eq,z are shown, respectively, in the center and bottom right-hand side of Fig. 2-18.

FIGURE 2-18: Schematic of a 3D IC integration of eight copper-filled TSV chips along with the equivalent thermal conductive model and boundary conditions.

First, construct the geometry of the copper-filled TSV chip with various diameters, pitches, and aspect ratios. Then input the thermal material properties [the thermal conductivity of silicon is 150 W/(m • °C) and that of copper is 390 W/(m • °C)]. Finally, apply the kinetic and kinematic boundary conditions, and calculate the temperature distributions.

The equivalent thermal conductivity can be obtained with the equations shown in the lower left-hand corner of Fig. 2-18. For example, to extract the equivalent thermal conductivity in the z direction, the geometry of the TSV chip is constructed, then a uniform heat flux q is imposed on the top surface of the TSV chip, and the bottom surface is set as an isotherm boundary (i.e., 25°C), whereas the four surrounding boundaries are set as adiabatic boundaries. By using the Flowtherm software, the average temperature on the top surface of the TSV chip can be calculated, and consequently, k_eq,z can be obtained using the first equation in the figure.

FIGURE 2-19: The equivalent thermal conductivity (in the vertical direction) for a copper-filled TSV chip with various diameters, pitches, and aspect ratios.

Figures 2-19 and 2-20, respectively, show the equivalent thermal conductivity for k_eq,z and k _eq,x = k_eq,y of a copper-filled TSV chip with various diameters, pitches, and aspect ratios. It can be seen that (1) the equivalent thermal conductivity in all directions of the TSV chip is larger than that of a pure silicon chip, (2) the equivalent thermal conductivity in all directions is larger for smaller pitches of the TSV chip, and (3) the equivalent thermal conductivity in all directions is larger for larger diameters of the TSV chip. For engineering convenience, the results in Figs. 2-19 and 2-20 have been curve-fitted into the following empirical equations for equivalent thermal conductivity:

k_eq,z = 150 +188D^2p-2

k_eq,x = k_eq,y = 150 + 105D²p^-2

where P is the pitch, D = (D₁ + D₂)/2 is the diameter, and D1 and D2 are the diameters of a tapered TSV chip. The accuracy of these equations has been demonstrated by showing the correlation between the empirical equations (for the case of P = 0.3 mm) with the detailed 3D CFD analyses, as shown in Figs. 2-19 and 2-20. Consequently, these empirical equations will be used for TSV chips as a lumped block without any vias for analysis of the 3D SiP. Table 2-1 shows the material properties for the simulations.

FIGURE 2-20: The equivalent thermal conductivity (in the horizontal direction) for a copper-filled TSV chip with various diameters, pitches, and aspect ratios.

Thermal Performance of 3D Stacked TSV Chips with a Uniform
Heat Source

Figure 2-21 shows the maximum junction temperature of a stacked chip (varying with the number of the chips) package. In these simulations, all the chips have the same size (5 x 5 x 0.05 mm), and there are 225 (15 x 15) copper-filled TSVs with a 0.2-mm pitch on each chip. The power dissipated by each chip is 0.2 W, and it is assumed that the power is uniformly distributed on each chip. The ambient temperature is 25°C. It can be seen from the figure that the maximum junction temperature increases linearly with the number of the chips stacked. In addition, it can be seen that if the maximum allowable junction temperature is 85°C, then the maximum number of chips that can be stacked together is seven under the present conditions.

Figure 2-22 shows the maximum junction temperature at each layer of the TSV chip stack. It can be seen that the maximum junction temperature difference between each layer of the stack is negligible. This means that the temperature distribution for the different layer of chips is uniform because we assumed that the power dissipation is uniformly distributed in each chip.

TABLE 2-1: Material Properties and Dimensions of 3D IC Integration.

FIGURE 2-21: Maximum junction temperature of the eight stacked chips.

FIGURE 2-22: Maximum junction temperature at each layer of the TSV chip stack.

Figure 2-23 shows the variation in thermal resistance of the SiP with the number of the TSV chips stacked. The materials, geometry, boundary conditions, and assumptions are the same as those in Fig. 2-21. It can be seen that the thermal resistance of the stacked SiP decreases as the number of chip in the stack increases.

FIGURE 2-23: Variation in thermal resistance of the SiP with the number of TSV stacked chips.

Thermal Performance of 3D Stacked TSV Chips with a Nonuniform Heat Source

The results presented in Figures 2-21, 2-22, and 2-23 are based on the assumption that the power is dissipated uniformly over the whole chip. However, in most applications, the power dissipated by each chip is basically nonuniform, and as such, it will induce quite different thermal behaviors of the 3D IC SiP with TSV chips. In addition, it is well known that ordinary silicon chips normally have large parallel conduction of heat (parallel to the chip surface) owing to the large thermal conductivity of the Si material. However, for 3D IC chip stacking, in order to have a low profile, the chip thickness of each layer of the 3D SiP must be ground down to 50 um and less. Thus the parallel spreading effect is suppressed by the very thin chip, and the hot spot will be very intense. Compounding this with the nonuniform heat source, the hot spot becomes a challenge in 3D IC integration SiP.

Figures 2-24, 2-25, and 2-26 show the thermal performance of a 3D integration of two copper-filled TSV chips stacking in an SiP, where a single copper-filled TSV chip is also included. All the chips are 5 x 5 mm, and their thicknesses vary from 10 to 200 um. Each chip’s center is subjected to a distinct heat source (0.2 W) in a tiny area (0.2 x 02 mm). It can be seen from Figs. 2-24 and 2-25 that (for both one- and two-chip stacks) (1) for a nonuniform heat source, the effect of chip thickness on the thermal performance of 3D IC integrations is very important, (2) this thickness effect is even more significant in the application range (?50 um) of 3D IC integrations, and (3) the maximum junction temperature and thermal resistance decrease as chip thickness increases.

FIGURE 2-24: Maximum junction temperature of a 3D integration of two Cu-filled TSV chips.

FIGURE 2-25: Thermal resistance of a 3D integration of two Cu-filled TSV chips.

Figure 2-26 shows the temperature maps on the chip for various chip thicknesses. It can be seen that the heat on the chip surface is well dissipated for typical chip thicknesses of 100 to 200 um subjected to a generated power of 0.2 W. For the 200-um-thick chip, the temperature distribution is almost uniform and equal to 35°C. However, the hot-spot temperature on the chip increases to 69°C (0.2-W power) if the chip thickness is reduced to 10 um, and the hot-spot area is clearly shown.

FIGURE 2-26: Temperature maps on the chip for various chip thicknesses (hot spots).

In addition to one heat source per chip (5 x 5 mm), Figs. 2-27 and 2-28 show the effect of two heat sources at a distance apart (gap) on the thermal performance of 3D IC integrations of copper-filled TSV chips. There are two distinct heat sources (each with 0.1 W and on 0.2 x 0.2 mm area) on each chip (5 x 5 x 0.05 mm). It can be seen from the figures that (1) the larger the gap (b/a ?0.7) between the two heat sources, the better is the thermal performance (i.e., lower maximum junction temperature and thermal resistance), and (2) when the gap between the two heat sources is larger than 0.7 (i.e., the heat sources are too close to the edge of the chip), the thermal performance is weaker. This is due to suppressible spreading effects near the edges of the chips.

FIGURE 2-27: Maximum junction temperature of a 3D integration of two Cu-filled TSV chips subjected to two distinct heat sources.

FIGURE 2-28: Thermal resistance of a 3D integration of two Cu-filled TSV chips subjected to two distinct heat sources.

In addition to the case of overlapping heat sources discussed in the preceding paragraph, finally, Figs. 2-29 and 2-30 show the orientation effect (staggered heat sources) of two stacked chips, each with two heat sources at a certain distance apart, on the thermal performance of a 3D SiP. It can be seen that (1) similar to case of overlapping heat sources, the larger the gap (b/a ?0.7) between those two pairs of staggered heat sources, the lower are the maximum junction temperature and thermal resistance, (2) when the gap between the two pairs of staggered heat sources is larger than 0.7 (i.e., the heat sources are too close to the edge of the chip), the thermal performance is weaker, and (3) the maximum junction temperature and thermal resistance of the 3D SiP with two TSV chips subjected to two pairs of staggered heat sources are lower than those with two pairs of overlapping heat sources. This is so because the staggered heat sources avoid the superimposition of heat sources and thus lead to better thermal performance. This result is very useful for the design and layout 3D SiP because it permits relocation of the heat sources and/or rotation of the chip.

FIGURE 2-29: Maximum junction temperature of a 3D integration of two Cu-filled TSV chips subjected to two distinct staggered heat sources.

FIGURE 2-30: Thermal resistance of a 3D integration of two Cu-filled TSV chips subjected to two distinct staggered heat sources.

Editor’s notes:

– Part 1 of 3: Trends in advanced IC packaging

– Part 3 of 3: Trends in advanced IC Packaging

– All references will be provided in Part 3.

– Click here for additional information about the book or to purchase.

Excerpted from Advanced MEMS Packaging by John Lau, et al (McGraw-Hill; 2009) with permission from McGraw-Hill.

Tags: 3D IC Stacking, Advanced IC Packaging, Advanced MEMS Packaging, IBM, IC, IC Packaging, Intel, MEMS, MEMS Devices, MEMS Packaging

This entry was posted on Friday, February 19th, 2010 at 9:15 pm and is filed under Design, Feature. You can follow any responses to this entry through the RSS 2.0 feed.