Touch user interfaces have made significant advances in the consumer electronics market particularly for mobile phones and notebook computers, opening the door for adoption in other applications including white goods, computer peripherals, medical equipment, and instrumentation. Synaptics made its debut in the home appliance market earlier this year with the launch of the Samsung Hauzen ZERO air conditioner.
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Smaller distributors were the only ones to post sales gains in 2009. Interestingly, two of the five distributors that posted growth last year -- Interstate Connecting Components and Sherburn Electronics -- derive 100 percent of their sales from interconnect products. Both of them also target the military/aerospace industry. Here are the top 10 sales leaders by ICs, passives/electromechanical devices, interconnects and computer products as well as sales growth.
Part 1 of 3: Trends in advanced IC packaging
Here’s a book excerpt from Advanced MEMS Packaging, written by experts in the field. The book details the latest cutting-edge MEMS packaging techniques such as low-temperature bonding and 3-D packaging. It can certainly serve as a valuable reference for those faced with the challenging problems created by MEMS devices and packaging. Parts 1 & 2 cover advanced IC packaging, while part 3 addresses advanced MEMS packaging.
CHAPTER 2: Advanced MEMS Packaging
2.1 Introduction
This chapter briefly discusses the state of the art and future trends in
advanced integrated circuit (IC) electronics packaging, followed by a
discussion of advanced microelectromechanical systems (MEMS)
packaging, where 10 different designs of three-dimensional (3D)
MEMS packaging will be presented.
2.2 Advanced IC Packaging
3D IC integration with wafer-level packaging (WLP) has been the hottest packaging technology in the past few years and will be the trend in the future. The supply chain of 3D IC integration and WLP includes semiconductor device designers, foundries, packaging and testing houses, electronic design automation (EDA) vendors, processing equipment suppliers, materials suppliers, universities and research institutes, and industry analysts. In this section, the Moore’s law versus more than Moore (MTM) will be discussed briefly first. Next, some of the critical issues of 3D IC integration will be presented. Finally, a couple of enabling technologies (e.g., microbumps and thermal management) for 3D IC integration with WLP will be provided.
2.2.1 Moore’s Law versus More Than Moore (MTM)
In April 1965, Moore published a paper in Electronics with the title, “Cramming More Components onto Integrated Circuits.” Based on a few data points (Figs. 2-1 and 2-2), Moore proposed to put more transistors on an IC by reducing the feature sizes. Further, he suggested that the number of transistors on an IC (for minimum cost) doubles every 24 months. In the past 40+ years, Moore’s observation (law) about silicon integration (i.e., cost, yield, and reliability) has been the most powerful driver for development of the microelectronics industry. This law places emphasis on lithography scaling and integration [in two dimensions (2D)] of all functions on a single chip, perhaps through system-on-chip (SoC) capabilities. Today, 32-nm ICs are in volume production, and production of 28-nm ICs is planned to begin in the second half of 2010. In the meantime, 22-nm technology has been working/performing very well in research institutions and laboratories.
FIGURE 2-1: The empirical observation made by Moore in 1965 that the number of transistors on an IC for minimum component cost doubles every 24 months.
FIGURE 2-2: Moore
FIGURE 2-3: The accelerometer MEMS device is integrated into the ASIC chip by Analog Devices. On the other hand, the same functions can be achieved by stacking the MEMS device on the ASIC chip, resulting in 3D MEMS packaging.
On the other hand, integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration and WLP, which is called more than Moore (MTM).1–54 Figure 2-3 shows an example of Moore’s law (2D) versus MTM (3D). It can be seen from the left side of the figure that the accelerometer MEMS device is integrated into the ASIC chip by Analog Devices. On the other hand, the same functions can be achieved by stacking the MEMS device on the ASIC chip,52–54 resulting in 3D MEMS packaging (or 3D MEMS SiP or 3D MEMS WLP), which is the focus of this book.
It should be pointed out that MTM is much more than just SiP. Based on the silicon-platform technology, anything that involves the integration of electronics, photonics, mechanics, chemistry, heat, magnetics, biology, etc., for functionality and system performance when interacting with people and the environment can be called MTM. One of the reasons why MEMS is called MTM is because the microelectronic ICs are thought of as the “brains” of a system, and MEMS augments this decision-making capability with “eyes” and “arms” to allow microsystems to sense and control the environment.
2.2.2 3D IC Integration with WLP
The Holy Grail of 3D IC integration (heterogeneous integration) is shown in Fig. 2-4, where all the chips [e.g., microdisplay, MEMS, memory, microprocessor, multiple outputs dc-dc converter, digital signal processor, microbattery, and analog-to-digital (A/D) mixed signal] are stacking in three dimensions. Just as with many other new technologies, 3D IC integration still faces many critical issues. In the development of 3D IC integration, the following must be noted and understood:1–24
FIGURE 2-4: The Holy Grail of 3D IC integration (heterogeneous integration) with TSV, which provides shorter wiring than 2D SoC.
- Design guidelines and software are not available.
- Test methods and equipment are lacking.
- Known good dies (KGDs) are required.
- Through-silicon vias (TSVs) with redistribution layers (RDLs)
usually are required. - Microbumps usually are required.
- Equipment accuracy is necessary for alignments.
- Fast chips must be mixed with slow chips.
- Large chips must be mixed with small chips.
- Wafer thinning and thin-wafer handling during processing
are necessary. - Thermal issues:
– The heat flux generated by stacked multifunctional chips
in miniature packages is extremely high.
– 3D circuits increase total power generated per unit surface
area.
– Chips in the 3D stack may be overheated if proper and
adequate cooling is not provided.
– The space between the 3D stack may be too small for cooling
channels (i.e., no gap for fluid flow).
– Thin chips may create extreme conditions for on-chip hot
spots. - 3D IC stacking inspection methodology is needed.
- 3D IC stacking expertise is lacking.
- 3D IC stacking infrastructure is lacking.
- 3D IC stacking standards are lacking.
In the past few years, some of these critical issues have been studied by a number of experts. Their results have already been disclosed in diverse journals or, more specifically, in the proceedings of many conferences, symposia, and workshops whose primary emphases have been on electrical packaging and interconnection. Consequently, there is no single source of information devoted to the state of the art of 3D IC integration with WLP technology. This section briefly mentions only microbumps and thermal management of 3D IC integration. The other important enabling technology (e.g., TSV; wafer thinning and thin-wafer handling; thin-wafer strengthening; wafer dicing; underfilling; lead-free soldering; low-temperature bonding; chip-to-chip (C2C), chip-to-wafer (C2W), and wafer-to-wafer (W2W) bonding; and in situ stress measurement for MEMS applications) will be discussed throughout the remaining chapters of this book.
Figure 2-5 shows a generic 3D IC packaging roadmap provided by IBM.1 It can be seen from the “Chip-to-chip/chip-to-wafer” line that microbumps are used for connecting the high-performance chips and the TSV silicon carrier (interposer) and the 3D TSV memory-chip stack.
Figure 2-6 shows Intel’s proposed roadmap of package-architecture transitions to address the memory-bandwidth challenge.14 It can be seen that 3D stacked-die multiple-chip packaging is needed to meet the performance requirements and that microbumps are used to connect the memory chip to the central processor unit (CPU).
FIGURE 2-5: IBM
FIGURE 2-6: Intel
2.2.3 Low-Cost Solder Microbumps for 3D IC SiP
The material used for connecting high-pin-count, small-pad, and finepitch chips can be either high-cost metal bumps (e.g., copper and gold) or low-cost solder bumps (e.g., tin). In this section, only low-cost solder microbumps will be discussed.
Figure 2-7 is a schematic of the 3D stacking of a memory chip and an Si carrier chip (could be the CPU) with TSV.21 There are more than 4000 solder microbumps between them, and their distribution is shown in Fig. 2-8. The functional bumps are concentrated in a very narrow strip with very fine pitches (?25 um) and small pads (?15 um), and the dummy bumps (to provide support during assembly and to absorb the stresses and strains of thermal-expansion mismatch between the Si chip and the copper-filled TSV chip) are around the edges.
FIGURE 2-7: Schematic of the 3D stacking of a memory chip and an Si carrier (could be a CPU) at 25 um pitch.
FIGURE 2-8: Distribution of solder microbumps/under-bump-metallurgy (UBM)
Figure 2-9 shows a schematic of the cross section of a solder microbump on an Si chip. It can be seen that it consists of the metal pad and a Ti (or Ta) adhesion layer, Cu seed layer, plated Cu layer, plated Sn layer, and passivation layer. Figure 2-10 shows a schematic of the cross section of an electroless Ni and immersion Au (ENIG) under-bump metallurgy (UBM) pad. It can be seen that it consists of the Al pad, Ni layer, Au layer, and two passivation layers.
FIGURE 2-9: Schematic of the cross section of a solder microbump on a Si chip.
FIGURE 2-10: Schematic of the cross section of the electroless Ni.
Figure 2-11 shows scanning electron microscope (SEM) images of the electroplated Cu-Sn solder microbumps on an Si chip, and Fig. 2-12 shows the Cu-Sn solder microbumps on an Si chip after reflow at 265°C. Figure 2-13 shows a focused-ion-beam (FIB) image of the Cu-Sn solder microbumps on an Si chip. It can be seen that nice and smooth Cu-Sn solder microbumps on a 25-um pitch and 15-um pad have been achieved.
FIGURE 2-11: SEM image of the electroplated Cu-Sn solder microbumps on an Si chip.
FIGURE 2-12: SEM image of the Cu-Sn solder microbumps on an Si chip after reflow at 265 degrees C.
FIGURE 2-13: FIB image of the Cu-Sn solder microbumps on an Si chip.
FIGURE 2-14: SEM image of ENIG UBM on an Si carrier.
Just as with ordinary solder bumps, there are two layers of intermetallic compounds (IMCs), the Cu3Sn and Cu6Sn5.
Figures 2-14 and 2-15 show, respectively, SEM and FIB images of the ENIG UBM on an Si carrier. It can be seen that the Ni layer is about 4 um thick and that there is no cracking around the edges of the passivations. A similar UBM has been made for a 15-um pitch and 8-um pad. In this case, the Ni layer is about 2 um thick.22
FIGURE 2-15: FIB image of ENIG UBM on an Si carrier.
FIGURE 2-16: SEM images of the assembly cross section of an Si chip and Si carrier (15 um pitch and 8 um pad).
Figure 2-16 shows the assembly of an Si chip and Si carrier with 15-um pitch and 8-um pad Cu-Sn solder microbumps. It can be seen from the cross section that the micro solder joints between these chips can be assembled properly and that the standoff is about 12 um, which is preferred for 3D IC stacking and SiP.
The effective thermal expansion coefficient of the Cu-filled TSV Si carrier (~10 x 10-6/°C) is larger than that (~2.5 x 10-6/°C) of the Si chip, and therefore, underfill may be necessary to ensure the reliability of the micro solder joint. Figure 2-17 shows an optical photograph of a cross section of underfill between these two chips. For results of shearing and thermal cycling tests for these micro solder joint assemblies, please see refs. 21 and 22, which demonstrate that these solder microbumps are adequate for most operating conditions.
FIGURE 2-17: Optical photograph of a cross section of the underfill between an Si chip and Si carrier.
Editor’s notes:
– Part 2 of 3: Trends in advanced IC packaging
– Part 3 of 3: Trends in advanced IC Packaging
– All references will be provided in Part 3.
– Click here for additional information about the book or to purchase.
Excerpted from Advanced MEMS Packaging by John Lau, et al (McGraw-Hill; 2009) with permission from McGraw-Hill.
NXP offers a low-power IC aimed at MPPT applications using PV cells or fuel cells. 
C&K Components offers a series of low-cost, miniature slide switches. The OS Series of RoHS-compliant switches feature a new high-temperature option for lead-free soldering.